From b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 2 Apr 2020 20:03:48 -0700 Subject: soc/intel/xeon_sp/cpx: set up cpus Set up cpus: * setup apic IDs. * setup MSR to enable fast string, speed step, etc. * Enable turbo Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40112 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/soc/intel/xeon_sp/cpx/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.inc') diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 54004a5be7..aca8572ed9 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) +subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc -- cgit v1.2.3