From d4efb330c1d87ac9f16be4e97b70797dcbe4e3bc Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 22 Jul 2020 12:39:40 -0700 Subject: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0. Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) (limited to 'src/soc/intel/xeon_sp/cpx/Kconfig') diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index bd1fa97239..93098e8250 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,10 +2,6 @@ if SOC_INTEL_COOPERLAKE_SP -config MAINBOARD_USES_FSP2_0 - bool - default y - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 @@ -25,18 +21,24 @@ config PCR_BASE_ADDRESS help This option allows you to select MMIO Base Address of sideband bus. -# currently FSP hardcodes [0fe800000;fe930000] for its heap config DCACHE_RAM_BASE hex - default 0xfe9a0000 + default 0xfe8b0000 config DCACHE_RAM_SIZE hex - default 0x60000 + default 0x170000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x10000 + default 0xA0000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. It needs to include FSP-M stack requirement and + CB romstage stack requirement. config CPU_MICROCODE_CBFS_LOC hex @@ -57,7 +59,7 @@ config HEAP_SIZE config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0x70000 + default 0xA0000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know -- cgit v1.2.3