From 17a798b68cc6d475d5d0c14e1a4a39b14754203c Mon Sep 17 00:00:00 2001 From: Rocky Phagura Date: Thu, 8 Oct 2020 13:32:41 -0700 Subject: soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura Signed-off-by: Christian Walter Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/xeon_sp/cpx/Kconfig') diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 28e7b83386..369d474552 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -78,6 +78,10 @@ config FSP_TEMP_RAM_SIZE documentation says this needs to be at least 128KiB, but practice show this needs to be 256KiB or more. +config IED_REGION_SIZE + hex + default 0x400000 + config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y -- cgit v1.2.3