From d3d50e027f8c5b4b2a19450fa89ed0e07d69ce8e Mon Sep 17 00:00:00 2001
From: Marc Jones <marcjones@sysproconsulting.com>
Date: Wed, 23 Sep 2020 16:23:41 -0600
Subject: soc/intel/xeon_sp/acpi: Add pch.asl

Add ASL for the PCH. Initially, this only contains
soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL
may be added in the future.

Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/acpi/pch.asl | 6 ++++++
 1 file changed, 6 insertions(+)
 create mode 100644 src/soc/intel/xeon_sp/acpi/pch.asl

(limited to 'src/soc/intel/xeon_sp/acpi')

diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/pch.asl
new file mode 100644
index 0000000000..98a5fdd50d
--- /dev/null
+++ b/src/soc/intel/xeon_sp/acpi/pch.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* This file should be included in the proper platform ACPI \_SB PCI scope */
+
+/* LPC 0:1f.0 */
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
-- 
cgit v1.2.3