From 5e521d7e623df9dd30d2b073a838e419b3d29904 Mon Sep 17 00:00:00 2001 From: Shuo Liu Date: Tue, 7 May 2024 23:15:29 +0800 Subject: soc/intel/xeon_sp: Add PCIe root port driver The driver sets ACPI names for PCIe root ports and its subordinate devices, and fill SSDT for them accordingly. SPR PCIe root port devices are initially supported. TEST=Build and boot on intel/archercity CRB Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/81567 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan --- src/soc/intel/xeon_sp/Makefile.mk | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/xeon_sp/Makefile.mk') diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 35b998c850..4f87367c5e 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -16,6 +16,7 @@ ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-y += numa.c ramstage-y += config.c +ramstage-y += pcie_root_port.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c -- cgit v1.2.3