From 8f89549d3c7d41643337662947cfdb2329bd030b Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 16 Jan 2020 11:16:45 -0800 Subject: soc/intel: Add Intel Xeon Scalable Processor support This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/intel/xeon_sp/Kconfig | 134 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 src/soc/intel/xeon_sp/Kconfig (limited to 'src/soc/intel/xeon_sp/Kconfig') diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig new file mode 100644 index 0000000000..8c355c4582 --- /dev/null +++ b/src/soc/intel/xeon_sp/Kconfig @@ -0,0 +1,134 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_INTEL_XEON_SP + bool + help + Intel Xeon SP support + +if SOC_INTEL_XEON_SP + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select POSTCAR_CONSOLE + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET + select PLATFORM_USES_FSP2_0 + select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS + select FSP_T_XIP + select FSP_M_XIP + select FSP_USE_REPO + select POSTCAR_STAGE + select IOAPIC + select PARALLEL_MP + select SMP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select COMMON_FADT + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SPI + select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_PCR + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + +# Fake FSP binary is used, as the current FSP binary for SKX-SP +# is an engineering build. It is not available to the public +# for now. +config FSP_FD_PATH + string "Location of FSP binary" + depends on FSP_USE_REPO + default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" + +config MAX_SOCKET + int + default 2 + +# For 2S config, the number of cpus could be as high as +# 2 threads * 20 cores * 2 sockets +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x200000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config MMCONF_BASE_ADDRESS + hex + default 0x80000000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + + +endif ## SOC_INTEL_XEON_SP -- cgit v1.2.3