From e5565c45cb71df105bc9ff1dc7572b4e749adaea Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Thu, 5 Mar 2020 11:54:47 +0530 Subject: soc/intel/{icelake, tigerlake}: Remove DDI A lane programming For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by default. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A(for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp and tglrvp compilation and boot. Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313 Reviewed-by: Nico Huber Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim Reviewed-by: Nick Vaccaro Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/graphics.c | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index fef17e17e8..4054bd549b 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -37,24 +36,6 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig -- cgit v1.2.3