From c5316ec4d675750f35ff1b383adacc2255e92d79 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 29 May 2020 15:20:56 -0600 Subject: soc/intel/common/block: Add new block DTT Intel Dynamic Tuning Technology is the name of a PCI device on some Intel SoCs. This minimal PCI driver is only used now for SSDT generation on TGL devices. Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c30519c2fa..091abb927f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA -- cgit v1.2.3