From c25c1ebd9ed54d9c70d4c247c71fc19259751413 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 24 Jul 2020 12:26:21 -0600 Subject: src: Update bare access to BOOL CONFIG_ vals to CONFIG() BOOL type Kconfig values should be used through the CONFIG() macro. These instances were not, so update them. Signed-off-by: Martin Roth Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/fsp_params.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index cf24021841..885a6f9df3 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -109,7 +109,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); params->SkipMpInit = 0; } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); } /* D3Hot and D3Cold for TCSS */ @@ -277,8 +277,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; - params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); /* Enable Hybrid storage auto detection */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite() -- cgit v1.2.3