From 8ebbe17b8613c9cf499ab7d5090ed4ee3356c1f9 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 21 Apr 2020 23:19:52 -0700 Subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects. BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful. Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) Reviewed-by: Kane Chen Reviewed-by: EricR Lai --- src/soc/intel/tigerlake/meminit.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 86645472aa..d44554af7e 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -16,6 +16,14 @@ #define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) +/* + * Translate DDR4 channel # to FSP UPD index # for the channel. + * Channel 0 -> Index 0 + * Channel 1 -> Index 4 + * Index 1-3 and 5-7 are unused. + */ +#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) + enum dimm_enable_options { ENABLE_BOTH_DIMMS = 0, DISABLE_DIMM0 = 1, @@ -378,7 +386,7 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, for (i = 0; i < DDR4_CHANNELS; i++) { ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); + init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); } /* -- cgit v1.2.3