From 8d0e77bbd4145e138ff43951c8543cea2c3dfd50 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 8 Dec 2021 10:40:02 -0700 Subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) Reviewed-by: Tim Crawford Reviewed-by: Cliff Huang Reviewed-by: Subrata Banik --- src/soc/intel/tigerlake/pcie_rp.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index a9a6c7f374..ceb85d8aed 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -4,6 +4,8 @@ #include #include +#define CPU_CPIE_VW_IDX_BASE 24 + static const struct pcie_rp_group pch_lp_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, @@ -49,3 +51,22 @@ enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) return PCIE_RP_UNKNOWN; } + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return -1; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_PEG1: + return CPU_CPIE_VW_IDX_BASE + 2; + case SA_DEVFN_PEG2: + return CPU_CPIE_VW_IDX_BASE + 1; + case SA_DEVFN_PEG3: + return CPU_CPIE_VW_IDX_BASE; + case SA_DEVFN_CPU_PCIE: + return CPU_CPIE_VW_IDX_BASE + 3; + default: + return -1; + } +} -- cgit v1.2.3