From 5c10704f58982d62a1326e5d6ff9956e0eaf6e16 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 26 Jul 2020 09:22:42 +0200 Subject: soc/intel/tigerlake: Simplify is-device-enabled checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify if-statements and use is_dev_enabled() where possible. Change-Id: I791273e5dd633cd1d6218b322106e2f62a393259 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/43897 Reviewed-by: Tim Wawrzynczak Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/acpi.c | 5 ++- src/soc/intel/tigerlake/fsp_params.c | 36 ++++------------ src/soc/intel/tigerlake/romstage/fsp_params.c | 60 ++++++++------------------- 3 files changed, 29 insertions(+), 72 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 235b2b3707..c7c544615e 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -187,7 +188,7 @@ static unsigned long soc_fill_dmar(unsigned long current) uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -200,7 +201,7 @@ static unsigned long soc_fill_dmar(unsigned long current) uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; - if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 885a6f9df3..79ce04b5a7 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -99,10 +99,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Check if IGD is present and fill Graphics init param accordingly */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { @@ -195,10 +192,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* SATA */ dev = pcidev_path_on_root(PCH_DEVFN_SATA); - if (!dev) - params->SataEnable = 0; - else { - params->SataEnable = dev->enabled; + params->SataEnable = is_dev_enabled(dev); + if (params->SataEnable) { params->SataMode = config->SataMode; params->SataSalpSupport = config->SataSalpSupport; memcpy(params->SataPortsEnable, config->SataPortsEnable, @@ -244,37 +239,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); - if (!dev) - params->PchLanEnable = 0; - else - params->PchLanEnable = dev->enabled; + params->PchLanEnable = is_dev_enabled(dev); /* CNVi */ dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); - if (dev) - params->CnviMode = dev->enabled; - else - params->CnviMode = 0; + params->CnviMode = is_dev_enabled(dev); /* VMD */ dev = pcidev_path_on_root(SA_DEVFN_VMD); - if (dev) - params->VmdEnable = dev->enabled; - else - params->VmdEnable = 0; + params->VmdEnable = is_dev_enabled(dev); /* THC */ dev = pcidev_path_on_root(PCH_DEVFN_THC0); - if (!dev) - params->ThcPort0Assignment = 0; - else - params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE; + params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; dev = pcidev_path_on_root(PCH_DEVFN_THC1); - if (!dev) - params->ThcPort1Assignment = 0; - else - params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE; + params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index b12faecd24..acb366bb4a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -21,16 +22,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t cpu_id, mask = 0; const struct device *dev; + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - } + m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -76,7 +74,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - if (dev && dev->enabled && config->TraceHubMode) { + if (is_dev_enabled(dev) && config->TraceHubMode) { m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; m_cfg->PchTraceHubMode = config->TraceHubMode; m_cfg->CpuTraceHubMode = config->TraceHubMode; @@ -87,10 +85,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (!dev || !dev->enabled) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = 1; + m_cfg->PchIshEnable = is_dev_enabled(dev); /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; @@ -119,39 +114,23 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TCSS DMA */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - if (dev) - m_cfg->TcssDma0En = dev->enabled; - else - m_cfg->TcssDma0En = 0; + m_cfg->TcssDma0En = is_dev_enabled(dev); dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); - if (dev) - m_cfg->TcssDma1En = dev->enabled; - else - m_cfg->TcssDma1En = 0; + m_cfg->TcssDma1En = is_dev_enabled(dev); /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); - if (dev) - m_cfg->TcssItbtPcie0En = dev->enabled; - else - m_cfg->TcssItbtPcie0En = 0; + m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + dev = pcidev_path_on_root(SA_DEVFN_TBT1); - if (dev) - m_cfg->TcssItbtPcie1En = dev->enabled; - else - m_cfg->TcssItbtPcie1En = 0; + m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); dev = pcidev_path_on_root(SA_DEVFN_TBT2); - if (dev) - m_cfg->TcssItbtPcie2En = dev->enabled; - else - m_cfg->TcssItbtPcie2En = 0; + m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); + dev = pcidev_path_on_root(SA_DEVFN_TBT3); - if (dev) - m_cfg->TcssItbtPcie3En = dev->enabled; - else - m_cfg->TcssItbtPcie3En = 0; + m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); /* Hyper Threading */ m_cfg->HyperThreading = !config->HyperThreadingDisable; @@ -167,10 +146,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaEnable = is_dev_enabled(dev); m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; -- cgit v1.2.3