From 591b0ff535d36f0f69e92c55fe465cbf70dcbfe4 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 8 Jan 2020 11:51:37 -0800 Subject: soc/intel/tigerlake: Configure ClkReq according to mainboard design BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 388ac42649..a4533c9e6c 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -60,12 +60,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PcieClkSrcUsage[i] = 0xff; } + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - /* UART Debug Log*/ + /* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; -- cgit v1.2.3