From 48c7870e5294336851472ac9eb1e4665715316f9 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 12 Dec 2019 10:37:49 +0530 Subject: soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT). Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/tigerlake/acpi.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 225f4e8211..5e04c9a3b5 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -171,16 +171,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt) config_t *config = config_of_soc(); - if (!config->PmTimerDisabled) { - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - } + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; -- cgit v1.2.3