From 3180af7fd6a86d202c241b02afa9cc4c0b9d9262 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 19 Mar 2020 15:30:06 -0700 Subject: soc/intel/tigerlake: Configure Hyperthreading Configure Hyperthreading based on devicetree BUG=none TEST= Build and boot with FSP log and check Hyperthread setting Signed-off-by: Wonkyu Kim Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 2 ++ src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f82f13d45b..1d4bd5fa5a 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -292,6 +292,8 @@ struct soc_intel_tigerlake_config { */ uint8_t cpu_ratio_override; + /* HyperThreadingDisable : Yes (1) / No (0) */ + uint8_t HyperThreadingDisable; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 95f637e4ec..32f1b031a9 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -143,8 +143,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, else m_cfg->TcssItbtPcie3En = 0; - /* Enable Hyper Threading */ - m_cfg->HyperThreading = 1; + /* Hyper Threading */ + m_cfg->HyperThreading = !config->HyperThreadingDisable; + /* Disable Lock PCU Thermal Management registers */ m_cfg->LockPTMregs = 0; /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ -- cgit v1.2.3