From 2980e317e3be99eef527a0578ae3a3982b2ccf40 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 17 Apr 2023 20:28:01 +0100 Subject: soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 2 -- src/soc/intel/tigerlake/fsp_params.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6aa040840e..3de8ffaf43 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -148,8 +148,6 @@ struct soc_intel_tigerlake_config { /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t TcssD3HotDisable; - /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t TcssD3ColdDisable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index b823f50301..358536ea43 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -327,7 +327,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = !config->TcssD3ColdDisable; + params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; -- cgit v1.2.3