From c332a47c54f6e9b025a36e14eb0d3b115400d21c Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 24 Jan 2020 17:02:08 -0800 Subject: soc/intel/tigerlake: Disable image clocks TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/tigerlake/romstage') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 6ed3dcd2de..9c105cadc2 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -102,6 +102,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ -- cgit v1.2.3