From 49111cd2ba12d33caa1031b5be6b631c9f76486a Mon Sep 17 00:00:00 2001 From: John Zhao Date: Fri, 3 Jan 2020 11:01:23 -0800 Subject: soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel/tigerlake/romstage') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 4b9b007eb6..072c99ea7e 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -131,6 +131,20 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + + /* Vt-D config */ + m_cfg->VtdDisable = 0; + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + m_cfg->VtdIopEnable = 0x1; + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + m_cfg->VtdItbtEnable = 0x1; + m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; + m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; + m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; + m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3