From 6ad8352a3de78e2f6869cc7fbc4274057fcffd4a Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 29 Apr 2020 19:49:25 -0700 Subject: src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M Due to refactoring of Serial IO code in FSP v3163 onwards we need to set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart initialization is skipped in FSP. This makes sure that SerialIo initialization in coreboot is not changed by FSP. BUG=b:155315876 BRANCH=none TEST=build and boot tglrvp/ripto/volteer and check UART debug logs Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899 Reviewed-by: Dossym Nurmukhanov Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/tigerlake/romstage/fsp_params.c') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 022cd830c9..e4f6e824c1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -82,6 +82,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, } m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); -- cgit v1.2.3