From 148f8397d2793a465623877d311733eb82e4fe69 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Thu, 18 Jun 2020 23:09:11 -0700 Subject: soc/intel/tigerlake: Disable CPU PCIe in FSP In TGL SoC we have PCH and CPU side PCIe support. This patch skips CPU side PCIe enablement in FSP if device is disabled in devicetree. Disabling the initialization of CPU PCIe saves ~30ms in FspSiliconInit! BUG=b:158573805 BRANCH=None TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch. Signed-off-by: Shaunak Saha Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/tigerlake/romstage/fsp_params.c') diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 4a45fd43ec..b12faecd24 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -217,6 +217,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); + m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- cgit v1.2.3