From dba6c4cfc08db8cb41b3f40d9ac9e03f92056046 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Fri, 17 Jan 2020 18:56:58 +0530 Subject: soc/intel/tigerlake: Update FSP params for Jasper Lake Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Reviewed-by: Rizwan Qureshi --- src/soc/intel/tigerlake/include/soc/pci_devs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc/intel/tigerlake/include') diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 9a35e73252..ef2dfe3ec4 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -86,6 +86,11 @@ #define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) +#endif + #define PCH_DEV_SLOT_SIO3 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) @@ -122,6 +127,12 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define PCH_DEV_SLOT_STORAGE 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#endif + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) -- cgit v1.2.3