From 8d9262a7e7c0b9ec8a48aee9792cef2bd15667d2 Mon Sep 17 00:00:00 2001
From: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Date: Tue, 3 Dec 2019 16:12:13 +0530
Subject: soc/intel/tigerlake: Pick correct pmc base reg from pch type

Update PMC shadow register base address for Jasperlake
Correct PCH detection logic based on PCH ids and return correct base
address based on PCH detected since our code supports both tgl and jsl.

Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
---
 src/soc/intel/tigerlake/include/soc/pch.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/soc/intel/tigerlake/include')

diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h
index 57ddeaf97f..ae8e310afb 100644
--- a/src/soc/intel/tigerlake/include/soc/pch.h
+++ b/src/soc/intel/tigerlake/include/soc/pch.h
@@ -18,8 +18,8 @@
 
 #include <stdint.h>
 
-#define PCH_H				1
-#define PCH_LP				2
+#define PCH_TGP				1
+#define PCH_JSP				2
 #define PCH_UNKNOWN_SERIES		0xFF
 
 #define PCIE_CLK_NOTUSED		0xFF
-- 
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