From 4b3e06edf2b7c2d99912038589764d551bc00c6f Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 11 May 2021 16:39:32 -0700 Subject: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design. BUG=b:184660529 TEST="emerge-volteer coreboot" compiles without error. Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/include/soc/usb.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc/intel/tigerlake/include') diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 5dea4bf52e..dc66556d06 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -137,4 +137,19 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } +struct tcss_port_config { + uint8_t enable; + uint8_t ocpin; +}; + +#define TCSS_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ +} + +#define TCSS_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ +} + #endif -- cgit v1.2.3