From 91e89c5393535406f98f0f05354459a123f0885b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 1 Nov 2019 18:30:01 +0530 Subject: soc/intel/tigerlake: Do initial SoC commit till ramstage Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar Reviewed-by: Rizwan Qureshi Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params.c | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 src/soc/intel/tigerlake/fsp_params.c (limited to 'src/soc/intel/tigerlake/fsp_params.c') diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c new file mode 100644 index 0000000000..18985a6495 --- /dev/null +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + /* TODO: Update with UPD override as FSP matures */ +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} -- cgit v1.2.3