From ec65adcf7e18fe91e7d4a0bfbebcdf50193de9a2 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 27 Apr 2020 17:13:41 -0700 Subject: soc/intel/tigerlake: Update C-State info C-State latency table was exposed by both intel-idle driver and BIOS/coreboot. And table in Kernel was used before. After kernel patch (https://patchwork.kernel.org/patch/11290319/), only BIOS/coreboot exposes C-State latency table through _CST. As current C-State latency table info is not correct for Tigerlake, update proper info according to BWG and reference code. - Update latency: CpuPowerMgmt.h Use BIOS reference code as values in BWG is not up-to-dated - Remove MSR program for latency: BWG 4.6.4.3.4 Reference: - TGL BWG #611569 Rev 0.7.6 - https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ ClientOneSiliconPkg/Cpu/Include/CpuPowerMgmt.h BUG=b:155223704 BRANCH=None TEST=Boot to OS and check C-State latency expected result >cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency} POLL C1_ACPI C2_ACPI C3_ACPI 0 1 253 1048 For detail, refer Bug info. Signed-off-by: Wonkyu Kim Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40816 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Nick Vaccaro Reviewed-by: Paul Menzel Reviewed-by: Srinidhi N Kaushik --- src/soc/intel/tigerlake/cpu.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) (limited to 'src/soc/intel/tigerlake/cpu.c') diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d33194e4c9..64ba2f9909 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -144,39 +144,6 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERF_BIAS, msr); } -static void configure_c_states(void) -{ - msr_t msr; - - /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - - /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -190,9 +157,6 @@ void soc_core_init(struct device *cpu) enable_lapic_tpr(); setup_lapic(); - /* Configure c-state interrupt response time */ - configure_c_states(); - /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); -- cgit v1.2.3