From 301b09b3e618b361502fa6065a28fa30d50e0c67 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 12 Aug 2021 10:49:58 -0600 Subject: soc/intel/tigerlake: Add TGL-H power limits Convert the power limit defines to an enum and add TGL-H entries. Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/tigerlake/chip.h') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index cc12da4a1a..966ce7c9c9 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -24,11 +24,15 @@ #define MAX_HD_AUDIO_SSP_LINKS 6 /* The first two are for TGL-U */ -#define POWER_LIMITS_U_2_CORE 0 -#define POWER_LIMITS_U_4_CORE 1 -#define POWER_LIMITS_Y_2_CORE 2 -#define POWER_LIMITS_Y_4_CORE 3 -#define POWER_LIMITS_MAX 4 +enum soc_intel_tigerlake_power_limits { + POWER_LIMITS_U_2_CORE, + POWER_LIMITS_U_4_CORE, + POWER_LIMITS_Y_2_CORE, + POWER_LIMITS_Y_4_CORE, + POWER_LIMITS_H_6_CORE, + POWER_LIMITS_H_8_CORE, + POWER_LIMITS_MAX +}; /* * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, -- cgit v1.2.3