From 9f0285b6fe46d6ec76faad0c099239c227e5caa1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 9 Jan 2022 02:20:17 +0100 Subject: soc/intel/tgl: deduplicate the PCIe root port map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/chip.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) (limited to 'src/soc/intel/tigerlake/chip.c') diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 6994d94c52..459452455c 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -17,19 +17,6 @@ #include #include -static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, - { 0 } -}; - -static const struct pcie_rp_group pch_h_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -170,10 +157,8 @@ void soc_init_pre_device(void *chip_info) soc_fill_gpio_pm_configuration(); /* Swap enabled PCI ports in device tree if needed. */ - if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)) - pcie_rp_update_devicetree(pch_h_rp_groups); - else - pcie_rp_update_devicetree(pch_lp_rp_groups); + const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups(); + pcie_rp_update_devicetree(pch_rp_groups); } static void cpu_fill_ssdt(const struct device *dev) -- cgit v1.2.3