From e7aa4541d432b3d543b55067dc277b77f0c18f8c Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Thu, 12 Aug 2021 10:49:58 -0600
Subject: soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-H

Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/soc/intel/tigerlake/bootblock/pch.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/tigerlake/bootblock')

diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 5cb3d630af..f613a959e2 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -28,7 +28,11 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1000
+#else
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1100
+#endif
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8
-- 
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