From d149bfa17fb1fca7e0a388fd6c0cbb088069d0d5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 22 Nov 2020 20:00:28 -0800 Subject: soc/intel: Configure P2SB before other PCH controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/bootblock/pch.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/tigerlake/bootblock') diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 18ca5e51af..5c4d1d5fb7 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -67,11 +67,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. -- cgit v1.2.3