From 954a5b50ad9d6ee31f0f0d7abe6badf412cbe9cc Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Mon, 16 Dec 2019 23:23:27 -0800
Subject: soc/intel/tigerlake: Update ACPI files

Add and update ACPI files for Tiger Lake SoC
Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl)

Reference
PCH EDS#576591 vol1 rev1.2
PCH EDS#575857 vol2 rev1.0

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/acpi/southbridge.asl | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/soc/intel/tigerlake/acpi/southbridge.asl')

diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 7de8ac42d3..8593d07326 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -25,8 +25,8 @@
 /* PCR access */
 #include <soc/intel/common/acpi/pcr.asl>
 
-/* eMMC, SD Card */
-#include "scs.asl"
+/* PCH clock */
+#include "camera_clock_ctl.asl"
 
 /* GPIO controller */
 #include "gpio.asl"
@@ -43,11 +43,11 @@
 /* Serial IO */
 #include "serialio.asl"
 
+/* SMBus 0:1f.4 */
+#include "smbus.asl"
+
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
-
-/* GBe 0:1f.6 */
-#include "pch_glan.asl"
-- 
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