From 2d0655008fa85d19c0c9e95dec9b26522fe2951f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 29 Apr 2020 12:40:08 -0700 Subject: soc/intel/tigerlake: Provide SoundWire controller properties The Intel Tigerlake SoundWire controller has 4 master links which are configured differently depending on the external crystal oscillator which is connected to the PCH. This function will read the PCH PMC EPOC register to determine the frequency and then fill out the master link entries with the correct table values. The frequency is also provided directly in a custom "ip-clock" property which will be added to the link descriptor and passed to the OS driver so it can know the clock rate of the master. BUG=b:146482091 Signed-off-by: Duncan Laurie Change-Id: I98b7df21210c29cd8defeff648f2c2207d629295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40889 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/tigerlake/Makefile.inc') diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 51422f9c64..9ff767cfec 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c +ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += me.c -- cgit v1.2.3