From dc08548ea87850507f496935bc05815645de7f61 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Wed, 15 Mar 2023 17:18:18 +0100 Subject: soc/intel/tigerlake: Enable early caching of RAMTOP region Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738 Reviewed-by: Subrata Banik Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/tigerlake/Kconfig') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fca4f794f6..9928591ab9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -93,7 +93,8 @@ config CPU_SPECIFIC_OPTIONS select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 select X86_CLFLUSH_CAR -- cgit v1.2.3