From d2132469ae86d7287576a2ba3211cdbfeb572703 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 15 May 2020 15:55:37 +0530 Subject: tigerlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on volteer system Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/tigerlake/Kconfig') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a690acf9dc..a55b543100 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER -- cgit v1.2.3