From 860c68449da9a6752fedb752cacdf0ac8bd6a61d Mon Sep 17 00:00:00 2001 From: Shreesh Chhabbi Date: Thu, 3 Dec 2020 15:06:20 -0800 Subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config option. Select CAR_HAS_SF_MASKS for Tigerlake. During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x are not being reset to default as per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5. Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient. Bug=b:171601324 BRANCH=volteer Test=Build and boot to ChromeOS on Delbin. Signed-off-by: Shreesh Chhabbi Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8 Signed-off-by: Shreesh Chhabbi Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/tigerlake/Kconfig') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7629c7e117..c7e10a9a69 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM + select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP -- cgit v1.2.3