From 4ed9f9a507a8b3419bc45431b8f1afb02c728a9e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 31 Oct 2020 22:01:55 +0530 Subject: soc/intel: Use of common reset code block This patch removes all redundant reset code block from each SoC and make use of common reset code block(fsp_reset.c) based on SOC_INTEL_COMMON_FSP_RESET. Respective SoC Kconfig to choose correct FSP global reset type as per FSP integration guide. Signed-off-by: Subrata Banik Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/tigerlake/Kconfig') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 79595269a2..492d6fd488 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -53,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_CAR -- cgit v1.2.3