From ff48b3b1ece1de71926a8f36ac71c1dddbc36b59 Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Wed, 12 Jul 2017 23:01:26 +0530 Subject: soc/intel/skylake: Enable SMBus based on mainboard config Enable SMBus controller based on config in mainboard devicetree.cb BUG=None TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run lspci in OS) based on board devicetree.cb config 'SmbusEnable'. Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1 Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/20546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik --- src/soc/intel/skylake/romstage/romstage_fsp20.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 1c63250d1f..9e871254cb 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -237,6 +237,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + mainboard_memory_init_params(mupd); } -- cgit v1.2.3