From ec1b37decc207f95f7d0cd9680d1f2aab4b9d1c5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 19 Feb 2021 20:28:20 +0100 Subject: soc/intel/{skl,icl}: Move tco_configure() to bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move tco_configure to bootblock) to other platforms. This is for consistency. Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946 Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/bootblock/bootblock.c | 4 ++++ src/soc/intel/skylake/romstage/pch.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 6380db2e1f..1e5f105274 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -33,4 +34,7 @@ void bootblock_soc_init(void) report_platform_info(); bootblock_pch_init(); gspi_early_bar_init(); + + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index c85bdd667f..f94d611abe 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void romstage_pch_init(void) { - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - /* Program SMBUS_BASE_ADDRESS and enable it */ smbus_common_init(); } -- cgit v1.2.3