From b5c5b9dc7cb211003d6a453167492eb25ec511c0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 Jul 2017 16:03:24 +0530 Subject: Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3" Don't need this additional 2ms delay as PCR read after sideband write help to fix original hard hang issue. This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e. Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20462 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/acpi/scs.asl | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 60c546b045..235a57e05c 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -86,7 +86,6 @@ Device (EMMC) /* Set bits 31, 6, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x80000045) - Sleep (2) /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) @@ -140,7 +139,6 @@ Device (SDXC) /* Set bits 8, 7, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x00000185) - Sleep (2) /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) -- cgit v1.2.3