From 9995418166bc4074de2a99aa50e74f8a88196c39 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 29 May 2019 23:33:06 +0200 Subject: soc/intel: Replace UART_BASE() and friends with a Kconfig Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident on APL at least. It is used outside of soc/intel/ scope, e.g. to con- figure SeaBIOS. As we only ever configure a single UART for the coreboot console, we don't need different addresses for each possible UART. Which saves us a lot of code. Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/skylake/Kconfig | 5 +++++ src/soc/intel/skylake/include/soc/iomap.h | 7 ------- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6591..626b5f80f0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -289,6 +289,11 @@ config CPU_BCLK_MHZ int default 100 +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe030000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 628a272a54..c73d766953 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -25,13 +25,6 @@ #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -#define UART_BASE_SIZE 0x1000 -#define UART_BASE_0_ADDRESS 0xfe030000 -/* Both UART BAR 0 and 1 are 4KB in size */ -#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ - UART_BASE_SIZE * (x))) -#define UART_BASE(x) UART_BASE_0_ADDR(x) - #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -- cgit v1.2.3