From 87ca3898f90a24c92e8dffb70d617049b05d190c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 19 Nov 2018 16:23:01 +0530 Subject: soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature This patch moves required Kconfig selection for enabling ASPM feature (like clk_pm, L1 state etc) from soc code to intel common pch base code. TEST=Run lspci -vvv | grep ASPM The output shows the ASPM L1 is enable for pci devices Change-Id: Ic77602a75f0c9ccf28ebfd57e53433dc90985a16 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/29653 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/skylake/Kconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ad5a754c1b..ae8253a53a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -40,10 +40,6 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_64MB select REG_SCRIPT select RTC -- cgit v1.2.3