From 5391e554e190d746ae54d09cd97c313736a04027 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 2 Jun 2017 12:16:04 -0500 Subject: soc/intel/common/block: add bios caching to fast spi module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik Reviewed-by: Philippe Mathieu-Daudé --- src/soc/intel/skylake/bootblock/cpu.c | 27 +-------------------------- 1 file changed, 1 insertion(+), 26 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 040e847e6c..dd51104b4d 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -17,10 +17,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -86,32 +84,9 @@ static void set_flex_ratio_to_tdp_nominal(void) soft_reset(); } -static void cache_bios_region(void) -{ - int mtrr; - size_t rom_size; - uint32_t alignment; - - mtrr = get_free_var_mtrr(); - - if (mtrr == -1) - return; - - /* Only the IFD BIOS region is memory mapped (at top of 4G) */ - rom_size = CONFIG_ROM_SIZE; - - if (!rom_size) - return; - - /* Round to power of two */ - alignment = 1 << (log2_ceil(rom_size)); - rom_size = ALIGN_UP(rom_size, alignment); - set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); -} - void bootblock_cpu_init(void) { - cache_bios_region(); + fast_spi_cache_bios_region(); /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); intel_update_microcode_from_cbfs(); -- cgit v1.2.3