From 3993d38ae6ea85a8d05349e6d7534f4cde9ba9ae Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 5 Apr 2021 11:40:11 +0200 Subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 0591348833f730a42e74039d8e2d957ec94a39d5 introduced this Kconfig option inside soc/intel/common scope. However, it was only hooked up in commit d74cd60b8159c3928dba318e6387f200ff3bb0e7 for Alder Lake, and in commit 99157c1f4a80556462ca22a4ade87b2c8d09e674 for Tiger Lake. Hook up the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which have the `InternalGfx` UPD. Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer Reviewed-by: Nico Huber Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index 2793c2db07..6c6e2e62c5 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -112,7 +112,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, const struct device *dev; dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = dev && dev->enabled; + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; /* * If iGPU is enabled, set IGD stolen size to 64MB. The FBC -- cgit v1.2.3