From 36ca7b3104301db721097ab1e4aebb4a6958725c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 23 Mar 2023 14:48:53 +0530 Subject: soc/intel: Move USB PORTSC definition into IA common code This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Angel Pons --- src/soc/intel/skylake/acpi/xhci.asl | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index e8c5ebf27e..0540919e37 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define PORTSCN_OFFSET 0x480 -#define PORTSCXUSB3_OFFSET 0x540 - -#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 -#define RO_BITS_OFF_MASK ~0x80FE0012 +#include /* * USB Port Wake Enable (UPWE) on usb attach/detach @@ -23,14 +19,8 @@ Method (UPWE, 3, Serialized) PSCT, 32, } Local0 = PSCT - /* - * And port status/control reg with RO and RWS bits - * RO bits: 0, 2:3, 10:13, 24, 28:30 - * RWS bits: 5:9, 14:16, 25:27 - */ - Local0 = Local0 & RO_BITS_OFF_MASK - /* Set WCE and WDE bits */ - Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE + Local0 = Local0 & PORTSCN_BITS_OFF_MASK + Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE PSCT = Local0 } -- cgit v1.2.3