From 360684b41aec795d254dcaac1cefb4acf9e129d3 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Thu, 18 Jun 2020 15:56:11 +0530 Subject: soc/intel/common: add TCC activation functionality This enables to configure the Thermal Control Circuit (TCC) activation value to new value as tcc_offset in degree Celcius. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action before CPU temperature reaches maximum operating temperature TjMax value. Also, cleanup local functions from previous intel soc specific code base like for apollolake, broadwell, skylake and cannonlake. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/skylake/cpu.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a545435599..d941df70b2 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,26 +27,6 @@ #include "chip.h" -static void configure_thermal_target(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~0x7f; /* Bits 6:0 */ - msr.lo |= 0xe6; /* setting 100ms thermal time window */ - wrmsr(MSR_TEMPERATURE_TARGET, msr); -} - static void configure_isst(void) { config_t *conf = config_of_soc(); @@ -333,7 +313,7 @@ void soc_init_cpus(struct bus *cpu_bus) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) -- cgit v1.2.3