From 1041d399cbbae9042a021502f9e105b078f5046e Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 2 Jun 2017 11:56:14 +0530 Subject: soc/intel/skylake: Add config for cpu base clock frequency Add config for cpu base clock frequency(Mhz) and replace current refrence from soc/cpu.h with config option. Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/20016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Kconfig | 4 ++++ src/soc/intel/skylake/acpi.c | 4 ++-- src/soc/intel/skylake/bootblock/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/skylake/include/soc/cpu.h | 3 --- src/soc/intel/skylake/tsc_freq.c | 3 +-- 6 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 80cdde63f8..067e833090 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -323,4 +323,8 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 2 +config CPU_BCLK_MHZ + int + default 100 + endif diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 77fbb48570..f9b39f28a0 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -410,7 +410,7 @@ static void generate_p_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * CPU_BCLK; + clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -474,7 +474,7 @@ static void generate_p_state_entries(int core, int cores_per_package) /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; + clock = ratio * CONFIG_CPU_BCLK_MHZ; acpigen_write_PSS_package( clock, /* MHz */ diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index dd51104b4d..6963b829ea 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -113,5 +113,5 @@ void set_max_freq(void) wrmsr(MSR_IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 057241327b..95d9ad9c8c 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -320,7 +320,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } static void set_energy_perf_bias(u8 policy) diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 9171172272..f6803c9e04 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -34,9 +34,6 @@ #define CPUID_KABYLAKE_HA0 0x506e8 #define CPUID_KABYLAKE_HB0 0x906e9 -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - /* Latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 diff --git a/src/soc/intel/skylake/tsc_freq.c b/src/soc/intel/skylake/tsc_freq.c index 9ebe3cb382..8a4ff461b2 100644 --- a/src/soc/intel/skylake/tsc_freq.c +++ b/src/soc/intel/skylake/tsc_freq.c @@ -17,7 +17,6 @@ #include #include #include -#include #include unsigned long tsc_freq_mhz(void) @@ -25,5 +24,5 @@ unsigned long tsc_freq_mhz(void) msr_t platform_info; platform_info = rdmsr(MSR_PLATFORM_INFO); - return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); + return CONFIG_CPU_BCLK_MHZ * ((platform_info.lo >> 8) & 0xff); } -- cgit v1.2.3