From 1d14b3e926c15027f9272f1e80b8913fef8cf25d Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Tue, 12 May 2015 18:23:27 -0700 Subject: soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/usbdebug.c | 51 ---------------------------------------- 1 file changed, 51 deletions(-) delete mode 100644 src/soc/intel/skylake/usbdebug.c (limited to 'src/soc/intel/skylake/usbdebug.c') diff --git a/src/soc/intel/skylake/usbdebug.c b/src/soc/intel/skylake/usbdebug.c deleted file mode 100644 index 736a1a3c44..0000000000 --- a/src/soc/intel/skylake/usbdebug.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -void set_debug_port(unsigned int port) -{ - /* Hardcoded to physical port 1 */ -} - -void enable_usbdebug(unsigned int port) -{ - u32 tmp32; - - tmp32 = pci_read_config32(PCH_DEV_EHCI, PCI_VENDOR_ID); - if (tmp32 == 0xffffffff || tmp32 == 0) - return; - - /* Set the EHCI BAR address. */ - pci_write_config32(PCH_DEV_EHCI, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY); - - /* Force ownership of the Debug Port to the EHCI controller. */ - tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); - tmp32 |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32); -} -- cgit v1.2.3