From 7e9cb9281581fdf1b75ef5e6f32a1ec322e11c8f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 Aug 2017 14:07:35 +0530 Subject: soc/intel/skylake: Add support for all UART port index Select LPSS UART Base address based on LPSS UART port index. Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20997 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/uart.c') diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 4e65859ea7..31389297b3 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -30,8 +30,8 @@ void pch_uart_read_resources(struct device *dev) if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ - res->base = UART_DEBUG_BASE_ADDRESS; - res->size = UART_DEBUG_BASE_SIZE; + res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + res->size = UART_DEBUG_BASE_0_SIZE; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -- cgit v1.2.3