From bf72dcbd2f1b0138a329f0c9adac33c387e8cd9f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 12 May 2020 16:04:47 +0200 Subject: soc/intel/common: Improve Type16 SMBIOS tables Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Christian Walter Reviewed-by: Philipp Deppenwiese --- src/soc/intel/skylake/systemagent.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel/skylake/systemagent.c') diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 8e58bf6669..f28bd257fe 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -87,3 +87,17 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; return 0; } + +uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) +{ + switch (capid0_a_ddrsz) { + case 1: + return 8192; + case 2: + return 4096; + case 3: + return 2048; + default: + return 32768; + } +} -- cgit v1.2.3