From f1db5fdb4d03b4766cf23e4b04a05b0fc05586a0 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@chromium.org>
Date: Tue, 2 May 2017 19:43:20 -0700
Subject: soc/intel/common: Provide common block fast_spi_flash_ctrlr

Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.

Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/skylake/spi.c | 19 ++-----------------
 1 file changed, 2 insertions(+), 17 deletions(-)

(limited to 'src/soc/intel/skylake/spi.c')

diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c
index e11e13f763..e575e6e265 100644
--- a/src/soc/intel/skylake/spi.c
+++ b/src/soc/intel/skylake/spi.c
@@ -20,28 +20,13 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/spi.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <soc/ramstage.h>
 #include <spi-generic.h>
 
-/* SPI controller managing the flash-device SPI. */
-static int flash_spi_ctrlr_setup(const struct spi_slave *dev)
-{
-	if ((dev->bus != 0) || (dev->cs != 0)) {
-		printk(BIOS_ERR, "%s: Unsupported device bus=0x%x,cs=0x%x!\n",
-			__func__, dev->bus, dev->cs);
-		return -1;
-	}
-
-	return 0;
-}
-
-static const struct spi_ctrlr flash_spi_ctrlr = {
-	.setup = flash_spi_ctrlr_setup,
-};
-
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{ .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
+	{ .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
 #if !ENV_SMM
 	{ .ctrlr = &gspi_ctrlr, .bus_start = 1,
 	  .bus_end =  1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
-- 
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