From fd8e00092a7d2b5ccc9bb832a8eafa2f2d1cddbf Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 17 May 2017 15:13:08 +0530 Subject: soc/intel/skylake: Use Intel SATA common code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use SATA common code from soc/intel/common/block/sata and clean up code. Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/19735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Philippe Mathieu-Daudé --- src/soc/intel/skylake/sata.c | 74 -------------------------------------------- 1 file changed, 74 deletions(-) delete mode 100644 src/soc/intel/skylake/sata.c (limited to 'src/soc/intel/skylake/sata.c') diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c deleted file mode 100644 index 277d6da246..0000000000 --- a/src/soc/intel/skylake/sata.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -static void *get_ahci_bar(void) -{ - device_t dev = PCH_DEV_SATA; - uint32_t bar; - - bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - - return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); -} - -/* - * SATA Port control and Status. By default, the SATA ports are set (by HW) - * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial - * power on reset. When enabled by software as per SATA port mapping, - * the ports can transition between the on, partial and slumber states - * and can detect devices. When disabled, the port is in the off state and - * can't detect any devices. - */ -static void sata_final(device_t dev) -{ - void *ahcibar = get_ahci_bar(); - u32 port_impl, temp; - - dev = PCH_DEV_SATA; - /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + 0x0c) & 0x07; - /* Port enable */ - temp = pci_read_config32(dev, 0x92); - temp |= port_impl; - pci_write_config32(dev, 0x92, temp); - -} - -static struct device_operations sata_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .final = sata_final, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d03, /* SKL-U Base */ - 0x9d07, /* SKL-Y Premium, SKL-U Premium */ - 0x282a, /* KBL */ - 0 -}; - -static const struct pci_driver pch_sata __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -- cgit v1.2.3